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1 ltc2845 sn2845 2845fs features applicatio s u descriptio u typical applicatio u 3.3v software-selectable multiprotocol transceiver dte or dce multiprotocol serial interface with db-25 connector , ltc and lt are registered trademarks of linear technology corporation. n data networking n csu and dsu n data routers n software-selectable transceiver supports: rs232, rs449, eia530, eia530-a, v.35, v.36, x.21 n operates from single 3.3v supply with ltc2846 or a single 5v supply with 3.3v logic with ltc2847 n tuv rheinland of north america inc. certified net1, net2 and tbr2 compliant, report no.: tbr2/050101/02 n complete dte or dce port with ltc2846 or ltc2847 n available in a 36-lead narrow (0.209") ssop and 38-lead (7mm x 5mm) qfn package the ltc ? 2845 is a 5-driver/5-receiver multiprotocol trans- ceiver. the ltc2845 and ltc2846 form the core of a complete software-selectable dte or dce interface port that supports the rs232, rs449, eia530, eia530-a, v.35, v.36 or x.21 protocols. the ltc2845 operates from a 3.3v supply and supplies provided by the ltc2846. this part is available in a 36-lead ssop and 38-lead (7mm x 5mm) qfn package. the ltc2845 and ltc2847 in qfn packages offer the smallest multiprotocol serial port available. d2 d1 ltc2845 rts dtr dsr dcd cts d3 r2 r1 r3 ll ri tm rl txd scte txc rxc rxd 2 14 24 11 15 12 17 9 3 1 4 19 20 623 22 5 13 8 10 18 * 21 25 7 16 d4 d5 r4 r5 ltc2846 d1 d2 d3 r1 r2 r3 t t t t t *optional 2845 ta01 rts a (105) rts b dtr a (108) dtr b cts a (106) sg (102) shield (101) db-25 connector dcd a (109) dcd b dsr a (107) dsr b ll a (141) ri a (125) tm a (142) rl a (140) cts b scte b scte a (113) txd b txd a (103) txc a (114) txc b rxc a (115) rxc b rxd a (104) rxd b
2 ltc2845 sn2845 2845fs absolute m axi m u m ratings w ww u package/order i n for m atio n w u u (note 1) supply voltage v cc ....................................................... C0.3v to 6.5v v in ..................................................................... C 0.3v to 6.5v v ee ...................................................................... C10v to 0.3v v dd ..................................................................... C 0.3v to 10v input voltage transmitters ........................... C 0.3v to (v cc + 0.3v) receivers ............................................... C 18v to 18v logic pins .............................. C 0.3v to (v cc + 0.3v) output voltage transmitters .................. (v ee C 0.3v) to (v dd + 0.3v) receivers ................................. C 0.3v to (v in + 0.3v) the l denotes specifications which apply over the full operating tempera- ture range, otherwise specifications are at t a = 25 c. v cc = 5v, v in = 3.3v, v dd = 8v, v ee = C 7v for v.28, C 5.5v for v.10, v.11 (notes 2, 3) electrical characteristics symbol parameter conditions min typ max units supplies i cc v cc supply current (dce mode, rs530, rs530-a, x.21 modes, no load 2.7 ma all digital pins = gnd or v in ) rs530, rs530-a, x.21 modes, full load l 110 150 ma v.28 mode, no load l 13 ma v.28 mode, full load l 13 ma no-cable mode l 700 1400 m a short-circuit duration transmitter output ..................................... indefinite receiver output .......................................... indefinite v ee .................................................................. 30 sec operating temperature range ltc2845c ............................................... 0 c to 70 c ltc2845i ........................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c order part number ltc2845cg ltc2845ig 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 v cc v dd d1 d2 d3 r1 r2 r3 d4 r4 m0 m1 m2 dce/dte d4enb r4en r5 d5 v ee gnd d1 a d1 b d2 a d2 b d3/r1 a d3/r1 b r2 a r2 b r3 a r3 b d4 a r4 a r5 a d5 a v in v cc r1 d2 d1 d3 r3 g package 36-lead plastic ssop d5 r5 d4 r2 r4 t jmax = 125 c, q ja = 90 c/ w, q jc = 35 c/ w consult ltc marketing for parts specified with wider operating temperature ranges. order part number LTC2845CUHF ltc2845iuhf 13 14 15 16 top view uhf package 38-lead (7mm 5mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 d2 d3 r1 r2 r3 d4 r4 m0 m1 m2 nc dce/dte d1 b d2 a d2 b d3/r1 a d3/r1 b r2 a r2 b r3 a r3 b d4 a r4 a r5 a d1 v dd v cc v ee v ee gnd d1 a d4enb r4en r5 d5 v cc v in d5 a 23 22 21 20 9 10 11 12 39 t jmax = 125 c, q ja = 34 c/ w exposed pad is v ee (pin 39) must be soldered to pcb uhf part marking 2845 2845i
3 ltc2845 sn2845 2845fs the l denotes specifications which apply over the full operating tempera- ture range, otherwise specifications are at t a = 25 c. v cc = 5v, v in = 3.3v, v dd = 8v, v ee = C 7v for v.28, C 5.5v for v.10, v.11 (notes 2, 3) electrical characteristics symbol parameter conditions min typ max units i ee v ee supply current (dce mode, rs530, rs530-a, x.21 modes, no load 2 ma all digital pins = gnd or v in ) rs530, x.21 modes, full load 23 ma rs530-a, full load 34 ma v.28 mode, no load 1 ma v.28 mode, full load 12 ma no-cable mode 10 m a i dd v dd supply current (dce mode, rs530, rs530-a, x.21 modes, no load 0.3 ma all digital pins = gnd or v in ) rs530, rs530-a, x.21 modes, full load 0.3 ma v.28 mode, no load 1 ma v.28 mode, full load 13.5 ma no-cable mode 10 m a i vin v in supply current (dce mode, all modes except no-cable mode 650 m a all digital pins = gnd or v in ) p d internal power dissipation (dce mode, rs530, rs530-a, x.21 modes, full load 240 mw all digital pins = gnd or v in ) v.28 mode, full load 64 mw logic inputs and outputs v ih logic input high voltage l 2v v il logic input low voltage v cc = 5v l 0.8 v r4en when v cc = 3.3v 0.5 v i in logic input current d1, d2, d3, d4, d5 l 10 m a m0, m1, m2, dce, d4enb, r4en = gnd l C30 C75 C120 m a m0, m1, m2, dce, d4enb, r4en = v in l 10 m a v oh output high voltage i o = C3ma l 2.7 3 v v ol output low voltage i o = 1.6ma l 0.2 0.4 v i osr output short-circuit current 0v v o v in l 50 ma i ozr three-state output current m0 = m1 = m2 = v in , v o = gnd l C30 C85 C160 m a m0 = m1 = m2 = v in , v o = v in l 10 m a v.11 driver v odo open circuit differential output voltage r l = 1.95k (figure 1) l 5v v odl loaded differential output voltage r l = 50 w (figure 1) 0.5v odo 0.67v odo v l 2v d v od change in magnitude of differential r l = 50 w (figure 1) l 0.2 v output voltage v oc common mode output voltage r l = 50 w (figure 1) l 3v d v oc change in magnitude of common mode r l = 50 w (figure 1) l 0.2 v output voltage i ss short-circuit current v out = gnd 150 ma i oz output leakage current C0.25v v o 0.25v, power off or l 1 100 m a no-cable mode or driver disabled t r , t f rise or fall time ltc2845c (figures 2, 5) l 21525ns ltc2845i (figures 2, 5) l 21535ns t plh input to output ltc2845c (figures 2, 5) l 20 40 65 ns ltc28451 (figures 2, 5) l 20 40 75 ns t phl input to output ltc2845c (figures 2, 5) l 20 40 65 ns ltc2845i (figures 2, 5) l 20 40 75 ns d t input to output difference, ? t plh C t phl ? ltc2845c (figures 2, 5) l 0312ns ltc2845i (figures 2, 5) l 0317ns t skew output to output skew (figures 2, 5) 3 ns
4 ltc2845 sn2845 2845fs the l denotes specifications which apply over the full operating tempera- ture range, otherwise specifications are at t a = 25 c. v cc = 5v, v in = 3.3v, v dd = 8v, v ee = C 7v for v.28, C 5.5v for v.10, v.11 (notes 2, 3) electrical characteristics symbol parameter conditions min typ max units v.11 receiver v th input threshold voltage C7v v cm 7v l C0.2 0.2 v d v th input hysteresis C7v v cm 7v l 15 40 mv i in input current (a, b) C10v v a,b 10v l 0.66 ma r in input impedance C10v v a,b 10v l 15 30 k w t r , t f rise or fall time (figures 2, 6) 15 ns t plh input to output ltc2845c c l = 50pf (figures 2, 6) l 50 80 ns ltc2845i c l = 50pf (figures 2, 6) l 50 90 ns t phl input to output ltc2845c c l = 50pf (figures 2, 6) l 50 80 ns ltc2845i c l = 50pf (figures 2, 6) l 50 90 ns d t input to output difference, ? t plh C t phl ? ltc2845c c l = 50pf (figures 2, 6) l 0416ns ltc2845i c l = 50pf (figures 2, 6) l 0421ns v.10 driver v o output voltage open circuit, r l = 3.9k l 4 6v v t output voltage r l = 450 w (figure 3) l 3.6 v r l = 450 w (figure 3) 0.9v o i ss short-circuit current v o = gnd 150 ma i oz output leakage current C0.25v v o 0.25v, power off or l 0.1 100 m a no-cable mode or driver disabled t r , t f rise or fall time r l = 450 w , c l = 100pf (figures 3, 7) 2 m s t plh input to output r l = 450 w , c l = 100pf (figures 3, 7) 1 m s t phl input to output r l = 450 w , c l = 100pf (figures 3, 7) 1 m s v.10 receiver v th receiver input threshold voltage l C0.25 0.25 v d v th receiver input hysteresis l 25 50 mv i in receiver input current C10v v a 10v l 0.66 ma r in receiver input impedance C10v v a 10v l 15 30 k w t r , t f rise or fall time c l = 50pf (figures 4, 8) 15 ns t plh input to output c l = 50pf (figures 4, 8) 55 ns t phl input to output c l = 50pf (figures 4, 8) 109 ns d t input to output difference, ? t plh C t phl ? c l = 50pf (figures 4, 8) 60 ns v.28 driver v o output voltage open circuit l 10 v r l = 3k (figure 3) l 5 8.5 v i ss short-circuit current v o = gnd l 150 ma i oz output leakage current C0.25v v o 0.25v, power off or l 1 100 m a no-cable mode or driver disabled sr slew rate r l = 3k, c l = 2500pf (figures 3, 7) l 430v/ m s t plh input to output r l = 3k, c l = 2500pf (figures 3, 7) l 1.3 2.5 m s t phl input to output r l = 3k, c l = 2500pf (figures 3, 7) l 1.3 2.5 m s
5 ltc2845 sn2845 2845fs electrical characteristics typical perfor a ce characteristics uw data rate (kbd) i cc (ma) 140 135 130 125 120 115 110 105 2845 g01 10 100 1000 10000 data rate (kbd) 10 i ee (ma) 34 34 30 28 26 24 22 20 18 30 100 2845 g02 20 40 50 60 70 80 10 30 100 20 40 50 60 70 80 data rate (kbd) i dd (ma) 16 15 14 13 12 11 10 9 8 7 2845 g03 temperature ( c) ?0 i cc (ma) 125 120 115 110 105 100 95 20 60 2845 g04 20 0 40 80 100 40 20 60 20 0 40 80 100 40 20 60 20 0 40 80 100 temperature ( c) i ee (ma) 2845 g05 34.6 34.4 34.2 34.0 33.8 33.6 33.4 33.2 33.0 temperature ( c) i dd (ma) 2845 g06 13.9 13.8 13.7 13.6 13.5 13.4 13.3 13.2 13.1 t a = 25 c t a = 25 c t a = 25 c rs530, x.21 in dce mode (three v.11, two v.10 drivers with full load) i cc vs data rate v.28 in dce mode (five v.28 drivers with full load) i dd vs data rate rs530-a in dce mode (three v.10 drivers with full load) i ee vs data rate rs530, x.21 in dce mode (three v.11, two v.10 drivers with full load) i cc vs temperature v.28 in dce mode (five v.28 drivers with full load) i dd vs temperature rs530-a in dce mode (three v.10 drivers with full load) i ee vs temperature the l denotes specifications which apply over the full operating tempera- ture range, otherwise specifications are at t a = 25 c. v cc = 5v, v in = 3.3v, v dd = 8v, v ee = C 7v for v.28, C 5.5v for v.10, v.11 (notes 2, 3) note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device are negative. all voltages are referenced to device ground unless otherwise specified. note 3: all typicals are given for v cc = 5v, v in = 3.3v, v dd = 8v, v ee = C 7v for v.28, C 5.5v for v.10, v.11 and t a = 25 c. symbol parameter conditions min typ max units v.28 receiver v thl input low threshold voltage l 0.8 v v tlh input high threshold voltage l 2v d v th receiver input hysterisis l 0.1 0.3 v r in receiver input impedance C15v v a 15v l 357 k w t r , t f rise or fall time c l = 50pf (figures 4, 8) 15 ns t plh input to output c l = 50pf (figures 4, 8) l 60 100 ns t phl input to output c l = 50pf (figures 4, 8) l 150 500 ns
6 ltc2845 sn2845 2845fs v cc (pins 1, 19/pins 17, 36): positive supply for the transceivers. connect to v cc pin 8 on ltc2846 or to 5v supply. connect a 1 m f capacitor to ground. v dd (pin 2/pin 37): positive supply voltage for v.28. connect to v dd pin 7 on ltc2846 or 8v supply. connect a 1 m f capacitor to ground. d1 (pin 3/pin 38): ttl level driver 1 input. d2 (pin 4/pin 1): ttl level driver 2 input. d3 (pin 5/pin 2): ttl level driver 3 input. r1 (pin 6/pin 3): cmos level receiver 1 output. receiver outputs have a weak pull up to v in when high impedance. r2 (pin 7/pin 4): cmos level receiver 2 output. r3 (pin 8/pin 5): cmos level receiver 3 output. d4 (pin 9/pin 6): ttl level driver 4 input. r4 (pin 10/pin 7): cmos level receiver 4 output. m0 (pin 11/pin 8): ttl level mode select input 0. mode select inputs pull up to v in . m1 (pin 12/pin 9): ttl level mode select input 1. m2 (pin 13/pin 10): ttl level mode select input 2. dce/dte (pin 14/pin 12): ttl level mode select input. logic high enables driver 3. logic low enables receiver 1. d4enb (pin 15/pin 13): ttl level enable input. logic low enables driver 4. pulls up to v in . r4en (pin 16/pin 14): ttl level enable input. logic high enables receiver 4. pulls up to v in . r5 (pin 17/pin 15): cmos level receiver 5 output. pi n fu n ctio n s uuu d5 (pin 18/pin 16): ttl level driver 5 input. v in (pin 20/pin 18): positive supply for the receiver outputs. 3v v in 3.6v. connect a 1 m f capacitor to ground. d5 a (pin 21/pin 19): driver 5 inverting output. r5 a (pin 22/pin 20): receiver 5 inverting input. r4 a (pin 23/pin 21): receiver 4 inverting input. d4 a (pin 24/pin 22): driver 4 inverting input. r3 b (pin 25/pin 23): receiver 3 noninverting input. r3 a (pin 26/pin 24): receiver 3 inverting input. r2 b (pin 27/pin 25): receiver 2 noninverting input. r2 a (pin 28/pin 26): receiver 2 inverting input. d3/r1 b (pin 29/pin 27): receiver 1 noninverting input and driver 3 noninverting output. d3/r1 a (pin 30/pin 28): receiver 1 inverting input and driver 3 inverting output. d2 b (pin 31/pin 29): driver 2 noninverting output. d2 a (pin 32/pin 30): driver 2 inverting output. d1 b (pin 33/pin 31): driver 1 noninverting output. d1 a (pin 34/pin 32): driver 1 inverting output. gnd (pin 35/pin 33): ground. v ee (pin 36/pins 34, 35): negative supply voltage. con- nect to v ee pin 31 on ltc2846 or to C7v supply. connect a 1 m f capacitor to ground. exposed pad v ee (pin 39): must be soldered to pcb. (g-36/qfn-38 packages)
7 ltc2845 sn2845 2845fs block diagra w mode selection logic r2 r2a r2b r3 r3a r3b s3 20k 20k 20k 20k s3 10k 6k d3/r1 b 10k 10k 10k d3 dce/dte r1 d3 r1 6k 20k 20k s3 10k 10k 2845 bd 6k 7 8 5 6 28 27 d2 d2a d2b d2 4 32 31 d1 d1a d1b d1 3 v dd 2 v cc 1 gnd 35 v ee 36 34 33 26 25 29 s3 20k 20k 10k 6k d4a d4 r4 d4 9 10 m0 11 m1 12 m2 13 24 d5a d5 d5 18 21 r4a 23 v in 20 v cc 19 14 d4enb 15 r4en 16 r2 r3 r4 s3 10k 6k r5 17 r5 d3/r1 a 30 r5a 22 test circuits figure 3. v.10/v.28 driver test circuit a d 2845 f03 r l c l a d 2845 f04 c l r a figure 4. v.10/v.28 receiver test circuit figure 1. v.11 driver test circuit figure 2. v.11 driver/receiver ac test circuit a b 2845 f01 v od v oc r l r l a b a r b 2845 f02 r l 100 c l 100pf c l 100pf c l
8 ltc2845 sn2845 2845fs ode selectio w u (note 1) (note 4) (note 4) (note 1) d4a mode name m2 m1 m0 dce d1, d2, d3 d1 d2 d3 d5a /dte d4, d5 a b a b a b not used (default v.11) 0 0 0 0 ttl x v.11 v.11 v.11 v.11 z z v.10 rs530a 0 0 1 0 ttl x v.11 v.11 v.10 z z z v.10 rs530 0 1 0 0 ttl x v.11 v.11 v.11 v.11 z z v.10 x.21 0 1 1 0 ttl x v.11 v.11 v.11 v.11 z z v.10 v.35 1 0 0 0 ttl x v.28 z v.28 z z z v.28 rs449/v.36 1 0 1 0 ttl x v.11 v.11 v.11 v.11 z z v.10 v.28/rs232 1 1 0 0 ttl x v.28 z v.28 z z z v.28 no cable 1 1 1 0 x x z z z z z z z not used (default v.11) 0 0 0 1 ttl ttl v.11 v.11 v.11 v.11 v.11 v.11 v.10 rs530a 0 0 1 1 ttl ttl v.11 v.11 v.10 z v.11 v.11 v.10 rs530 0 1 0 1 ttl ttl v.11 v.11 v.11 v.11 v.11 v.11 v.10 x.21 0 1 1 1 ttl ttl v.11 v.11 v.11 v.11 v.11 v.11 v.10 v.35 1 0 0 1 ttl ttl v.28 z v.28 z v.28 z v.28 rs449/v.36 1 0 1 1 ttl ttl v.11 v.11 v.11 v.11 v.11 v.11 v.10 v.28/rs232 1 1 0 1 ttl ttl v.28 z v.28 z v.28 z v.28 no cable 1 1 1 1 x x z z z z z z z mode name m2 m1 m0 dce /dte not used (default v.11) 0 0 0 0 rs530a 0 0 1 0 rs530 0 1 0 0 x.21 0 1 1 0 v.35 1000 rs449/v.36 1 0 1 0 v.28/rs232 1 1 0 0 no cable 1 1 1 0 not used (default v.11) 0 0 0 1 rs530a 0 0 1 1 rs530 0 1 0 1 x.21 0 1 1 1 v.35 1001 rs449/v.36 1 0 1 1 v.28/rs232 1 1 0 1 no cable 1 1 1 1 (note 2) (note 3) (note 2) (note 2) (note 2) (note 5) (note 3) (note 5) r1 r2 r3 r4a r1 r2, r3 a b a b a b r5a r4, r5 v.11 v.11 v.11 v.11 v.11 v.11 v.10 cmos cmos v.11 v.11 v.10 30k v.11 v.11 v.10 cmos cmos v.11 v.11 v.11 v.11 v.11 v.11 v.10 cmos cmos v.11 v.11 v.11 v.11 v.11 v.11 v.10 cmos cmos v.28 30k v.28 30k v.28 30k v.28 cmos cmos v.11 v.11 v.11 v.11 v.11 v.11 v.10 cmos cmos v.28 30k v.28 30k v.28 30k v.28 cmos cmos 30k 30k 30k 30k 30k 30k 30k z z 30k 30k v.11 v.11 v.11 v.11 v.10 z cmos 30k 30k v.10 30k v.11 v.11 v.10 z cmos 30k 30k v.11 v.11 v.11 v.11 v.10 z cmos 30k 30k v.11 v.11 v.11 v.11 v.10 z cmos 30k 30k v.28 30k v.28 30k v.28 z cmos 30k 30k v.11 v.11 v.11 v.11 v.10 z cmos 30k 30k v.28 30k v.28 30k v.28 z cmos 30k 30k 30k 30k 30k 30k 30k z z note 1: driver inputs are ttl level compatible. note 2: unused receiver inputs are terminated with 30k to ground. note 3: receiver outputs are cmos level compatible and have a weak pull-up to v in when z. note 4: driver 4 is enabled by d4enb=0 (pin 15). note 5: receiver 4 is enabled by r4en=1 (pin 16).
9 ltc2845 sn2845 2845fs switchi g ti e wavefor s uw w figure 6. v.11 receiver propagation delays v ih v il receiver threshold 1.65v receiver threshold 1.65v t phl v oh v ol a r t plh 2845 f08 figure 8. v.10, v.28 receiver propagation delays 3v 0v 1.5v 0v ?v 3v 1.5v 0v 3v ?v t phl t f v o ? o d a t plh t r 2845 f07 figure 7. v.10, v.28 driver propagation delays v od2 ? od2 0v 1.65v 0v 1.65v t plh v oh v ol b ?a r t phl 2845 f06 f = 1mhz : t r 10ns : t f 10ns input output figure 5. v.11 driver propagation delays 3v 1.5v 1.5v 50% 10% 90% t plh t r 0v v o v o ? o d b ?a a b t phl t skew t skew 2845 f05 1/2 v o f = 1mhz : t r 10ns : t f 10ns v diff = v(b) ?v(a) 50% 10% 90% t f
10 ltc2845 sn2845 2845fs applicatio n s i n for m atio n wu u u overview the ltc2846/ltc2845 or ltc2847/ltc2845 form the core of a complete software-selectable dte or dce inter- face port that supports the rs232, rs449, eia530, eia530- a, v.35, v.36 or x.21 protocols. cable termination is provided on-chip, eliminating the need for discrete de- signs. ltc2846 dte ltc2846 dce 2845 f09 d3 d3 r1 103 w 103 w 103 w r3 ltc2845 d3 d4 d2 r1 r2 r3 ll tm ri rl txc rxc rxd txd scte txc rxc rxd serial controller d2 103 w scte r2 d1 103 w txd r3 r1 d2 d1 ltc2845 r2 r1 r3 d2 d1 d4 d5 txd scte txc rxc rxd rts dtr dcd dsr cts ll tm rts dtr dcd dsr cts rts dtr dcd dsr cts ll tm ri rl ri rl serial controller r2 r4 d3 r4 r5 d5 r5 d1 figure 9. complete multiprotocol interface in eia530 mode a complete dce-to-dte interface operating in eia530 mode is shown in figure 9. the ltc2846 of each port is used to generate the clock and data signals. the ltc2845 is used to generate the control signals along with ll (local loop-back), rl (remote loop-back), tm (test mode) and ri (ring indicate). cable termination is used only for the clock and data signals because they must support v.11 cable termination. the control signals do not need any external resistors.
11 ltc2845 sn2845 2845fs applicatio n s i n for m atio n wu u u mode selection the interface protocol is selected using the mode select pins m0, m1 and m2 (see the mode selection table). for example, if the port is configured as a v.35 interface, the mode selection pins should be m2 = 1, m1 = 0, m0 = 0. for the control signals, the drivers and receivers will operate in v.28 (rs232) electrical mode. for the clock and data signals, the drivers and receivers will operate in v.35 electrical mode. the dce/dte pin will configure the port for dce mode when high, and dte when low. the interface protocol may be selected simply by plugging the appropriate interface cable into the connector. the mode pins are routed to the connector and are left uncon- nected (1) or wired to ground (0) in the cable as shown in figure 10. the internal pull-up current sources will ensure a binary 1 when a pin is left unconnected and that the ltc2846/ ltc2845 enters the no-cable mode when the cable is removed. in the no-cable mode the ltc2846/ltc2845 supply current drops to less than 1000 m a and all driver outputs are forced into a high impedance state. the mode selection may also be accomplished by using jumpers to connect the mode pins to ground or v in . cable termination traditional implementations have included switching resistors with expensive relays, or required the user to change termination modules every time the interface standard has changed. custom cables have been used with the termination in the cable head or separate termina- tions are built on the board and a custom cable routes the signals to the appropriate termination. switching the termination with fets is difficult because the fets must remain off even though the signal voltage is beyond the supply voltage for the fet drivers or the power is off. using the ltc2846/ltc2845 solves the cable termination switching problem. via software control, appropriate ter- mination for the v.10 (rs423), v.11 (rs422), v.28 (rs232) and v.35 electrical protocols is chosen. v.10 (rs423) interface a typical v.10 unbalanced interface is shown in figure 11. a v.10 single-ended generator output a with ground c is connected to a differential receiver with inputs a ' con- nected to a, and input c ' connected to the signal return ground c. usually, no cable termination is required for v.10 interfaces, but the receiver inputs must be compliant with the impedance curve shown in figure 12. figure 10. single port dce v.35 mode selection in the cable nc nc v in cable 3.3k 2845 f10 ltc2846 ltc2845 connector (data) m0 m1 m2 dce/dte dce/dte m2 m1 m0 d4enb r4en (data)
12 ltc2845 sn2845 2845fs the v.10 receiver configuration in the ltc2845 is shown in figure 13. in v.10 mode switch s3 inside the ltc2845 is turned off. the noninverting input is disconnected inside the ltc2845 receiver and connected to ground.the cable termination is then the 30k input impedance to ground of the ltc2845 v.10 receiver. applicatio n s i n for m atio n wu u u figure 12. v.10 receiver input impedance figure 13. v.10 receiver configuration figure 14. typical v.11 interface i z v z 10v ?.25ma 3.25ma ?v 3v 10v 2845 f12 r5 20k ltc2845 receiver 2845 f13 a ' b ' c ' r8 6k s3 r6 10k r7 10k gnd r4 20k aa ' b c b ' c ' generator balanced interconnecting cable load cable termination receiver 100 min 2845 f14 aa ' cc ' generator balanced interconnecting cable load cable termination receiver 2845 f11 figure 11. typical v.10 interface figure 15. v.11 receiver configuration 1 actually, there is no switch s1 in receivers r2 and r3. however, for simplicity, all termination networks on the ltc2846 can be treated identically if it is assumed that an s1 switch exists and is always closed on the r2 and r3 receivers. r3 124 w r5 20k ltc2846 receiver 2845 f15 a ' b ' c ' r1 51.5 w r8 6k s2 s3 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 v.11 (rs422) interface a typical v.11 balanced interface is shown in figure 14. a v.11 differential generator with outputs a and b with ground c is connected to a differential receiver with ground c ' , inputs a ' connected to a, b ' connected to b. the v.11 interface has a differential termination at the receiver end that has a minimum value of 100 w . the termination resistor is optional in the v.11 specification, but for the high speed clock and data lines, the termination is required to prevent reflections from corrupting the data. the receiver inputs must also be compliant with the imped- ance curve shown in figure 12. in v.11 mode, all switches are off except s1 of the ltc2846s receivers which connects a 103 w differential termination impedance to the cable as shown in fig- ure 15 1 . the ltc2845 only handles control signals, so no termination other than its v.11 receivers 30k input imped- ance is necessary.
13 ltc2845 sn2845 2845fs applicatio n s i n for m atio n wu u u figure 16. typical v.28 interface aa ' cc ' generator balanced interconnecting cable load cable termination receiver 2845 f16 figure 17. v.28 receiver configuration r5 20k ltc2845 receiver 2845 f17 r8 6k s3 r6 10k r7 10k r4 20k a ' b ' c ' gnd v.28 (rs232) interface a typical v.28 unbalanced interface is shown in figure 16. a v.28 single-ended generator output a with ground c is connected to a single-ended receiver with input a ' con- nected to a, ground c ' connected via the signal return ground c. in v.28 mode, all switches are off except s3 inside the ltc2846/ltc2845 which connects a 6k (r8) impedance to ground in parallel with 20k (r5) plus 10k (r6) for a combined impedance of 5k as shown in figure 17. the noninverting input is disconnected inside the ltc2846/ ltc2845 receiver and connected to a ttl level reference voltage for a 1.4v receiver trip point. v.35 interface a typical v.35 balanced interface is shown in figure 18. a v.35 differential generator with outputs a and b with figure 19. v.35 receiver configuration figure 18. typical v.35 interface a a ' b c b ' c ' generator balanced interconnecting cable load cable termination receiver 2845 f18 50 125 50 50 125 50 r3 124 w r5 20k ltc2846 receiver 2845 f19 a ' b ' c ' r1 51.5 w r8 6k s2 s3 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 ground c is connected to a differential receiver with ground c ' , inputs a ' connected to a, b ' connected to b. the v.35 interface requires a t or delta network termination at the receiver end and the generator end. the receiver differential impedance measured at the connector must be 100 w 10 w , and the impedance between shorted termi- nals (a ' and b ' ) and ground c ' must be 150 w 15 w . in v.35 mode, both switches s1 and s2 inside the ltc2846 are on, connecting the t network impedance as shown in figure 19. the 30k input impedance of the receiver is placed in parallel with the t network termination, but does not affect the overall input impedance significantly. the generator differential impedance must be 50 w to 150 w and the impedance between shorted terminals (a and b) and ground c must be 150 w 15 w . for the generator termination, switches s1 and s2 are both on as shown in figure 20.
14 ltc2845 sn2845 2845fs dte vs dce operation the dce/dte pin acts as an enable for driver 3/receiver 1 in the ltc2846, and driver 3/receiver 1 in the ltc2845. the ltc2846/ltc2845 can be configured for either dte or dce operation in one of two ways: a dedicated dte or dce port with a connector of appropriate gender, or a port with one connector that can be configured for dte or dce operation by rerouting the signals to the ltc2846/ltc2845 using a dedicated dte cable or dedicated dce cable. a dedicated dte port using a db-25 male connector is shown in figure 23. the interface mode is selected by logic outputs from the controller or from jumpers to either v in or gnd on the mode select pins. a dedicated dce port using a db-25 female connector is shown in figure 24. a port with one db-25 connector, can be configured for either dte or dce operation is shown in figure 25. the configuration requires separate cables for proper signal routing in dte or dce operation. for example, in dte mode, the txd signal is routed to pins 2 and 14 via driver 1 in the ltc2846. in dce mode, driver 1 now routes the rxd signal to pins 2 and 14. compliance testing the ltc2846/ltc2845 chipset has been tested by tuv rheinland of north america inc. and passed the net1, net2 and tbr2 requirements. copies of the test report are available from ltc or tuv rheinland of north america inc. the title of the report is test report no.tbr2/050101/02 the address of tuv rheinland of north america inc. is: tuv rheinland of north america inc. 1775, old highway 8 nw, suite 107 st. paul, mn 55112 tel. (651) 639-0775 fax (651) 639-0873 no-cable mode the no-cable mode (m0 = m1 = m2 = d4enb = 1, r4en = 0) is intended for the case when the cable is disconnected from the connector. the bias circuitry, drivers and receiv- ers are turned off, the driver outputs are forced into a high impedance state, and the supply current drops to less than 700 m a. ltc2846 and ltc2847 supplies the ltc2846 and ltc2847 use an internal capacitive charge pump to generate v dd and v ee as shown in figure 21. a voltage doubler generates about 8v on v dd and a voltage inverter generates about C 7.5v for v ee . three 1 m f surface mounted tantalum or ceramic capacitors are re- quired for c1, c2 and c3. the v ee capacitor c4 should be a minimum of 3.3 m f. all capacitors are 16v and should be placed as close as possible to the ltc2846 to reduce emi. the ltc2846 has an internal boost switching regulator which generates a 5v output from the 3.3v supply as shown in figure 22. the 5v v cc supplies its internal charge pump and transceivers as well as its companion chip. the ltc2847 requires an external 5v supply. receiver fail-safe all ltc2846/ltc2845 receivers feature fail-safe opera- tion in all modes. if the receiver inputs are left floating or shorted together by a termination resistor, the receiver output will always be forced to a logic high. applicatio n s i n for m atio n wu u u 2845 f21 c3 1 f c5 10 f 5v c1 1 f c2 1 f c4 3.3 f ltc2846 or ltc2847 v dd c1 + c1 v cc c2 + c2 v ee gnd + figure 21. charge pump figure 22. ltc2846 boost switching regulator gnd v in sw shdn fb v in 3.3v 2845 f22 d1 l1 5.6 h r1 13k boost switching regulator c5 10 m f c6 10 f r2 4.3k v cc 5v 480ma c1,c2: taiyo yuden x5r jmk316bj106ml d1: on semiconductor mbr0520 l1: sumida cr43-5r6 shdn figure 20. v.35 driver v.35 driver a b c 51.5 s2 s1 2845 f20 51.5 ltc2846 124
15 ltc2845 sn2845 2845fs figure 23. controller-selectable multiprotocol dte port with db-25 connector ltc2846 m0 m1 m2 dce/dte c2 1 f r1 13k c1 1 f c6 10 f c3 1 f c4 3.3 f v cc 5v shdn v in 3.3v charge pump boost switching regulator l1 5.6 h + d1 mbr0520 c5 10 f m0 m1 m2 d1 d2 d3 r1 r2 r3 t t t t t r2 4.3k v cc 5v v ee 7.5v v dd 8v d2 d1 ltc2845 d3 r2 r1 r4 r3 v cc v dd v ee gnd 2 14 24 11 15 12 17 9 3 1 4 19 20 8 23 10 6 22 5 13 7 16 2845 f23 txd a (103) txc a (114) txc b rxc a (115) rxc b rxd a (104) rxd b txd b scte a (113) scte b rts a (105) rts b dtr a (108) dtr b sg shield db-25 male connector dcd a (109) dcd b dsr a (107) dsr b cts a (106) cts b ri (125) d4 m0 m1 m2 dce/dte c9 1 f v in 3.3v c8 1 f c7 1 f rts dtr dsr dcd cts ri r5 tm (142) 25 tm 18 * ll (141) ll d5 21 rl (140) rl txd scte txc rxc rxd v in d4enb r4en nc v in 3.3v *optional c10 1 f typical applicatio n s u
16 ltc2845 sn2845 2845fs typical applicatio n s u ltc2846 m0 m1 m2 dce/dte c2 1 f r1 13k c1 1 f c6 10 f c3 1 f c4 3.3 f v cc 5v shdn v in 3.3v charge pump boost switching regulator l1 5.6 h + d1 mbr0520 c5 10 f m0 m1 m2 d1 d2 d3 r1 r2 r3 t t t t t r2 4.3k v cc 5v v ee 7.5v v dd 8v d2 d1 ltc2845 d3 r2 r1 r4 r3 v cc v dd v ee gnd 2 14 24 11 15 12 24 11 2 1 5 13 6 8 22 10 20 23 4 19 18 7 14 2845 f24 rxd a (104) txc a (114) txc b scte a (113) scte b txd a (103) txd b rxd b rxc a (115)b rxc b cts a (106) cts b dsr a (107) dsr b sg (102) shield (101) db-25 female connector dcd a (109) dcd b dtr a (108) dtr b rts a (105) rts b ll (141) d4 m0 m1 m2 dce/dte c9 1 f v in 3.3v c8 1 f c7 1 f cts dsr dtr dcd rts ll r5 rl (140) 21 rl * *optional ri (125) ri d5 25 tm (142) tm v in d4enb r4en nc nc nc v in 3.3v c10 1 f rxd rxc txc scte txd figure 24. controller-selectable dce port with db-25 connector
17 ltc2845 sn2845 2845fs typical applicatio n s u figure 25. controller-selectable multiprotocol dte/dce port with db-25 connector m0 m1 m2 dce/dte ltc2846 m0 m1 m2 dce/dte c2 1 f r1 13k c1 1 f c6 10 f c3 1 f c4 3.3 f v cc 5v shdn v in 3.3v charge pump boost switching regulator l1 5.6 h + d1 mbr0520 c5 10 f d1 d2 d3 r1 r2 r3 t t t t t r2 4.3k v cc 5v v ee 7.5v v dd 8v d2 d1 ltc2845 d3 r2 r1 r4 r3 v cc v dd v ee gnd 2 14 24 11 15 12 17 9 3 1 4 19 20 8 23 10 6 22 5 13 7 16 2845 f25 sg d4 m0 m1 m2 dce/dte c9 1 f v in 3.3v c8 1 f c7 1 f r5 25 18 * d5 21 dte_txd/dce_rxd dte_scte/dce_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd v in d4enb r4en nc *optional v in 3.3v c10 1 f txd a txc a txc b rxc a rxc b rxd a rxd b txd b scte a scte b rts a rts b dtr a dtr b sg shield dcd a dcd b dsr a dsr b cts a cts b ri rxd a dce dte txc a txc b scte a scte b txd a txd b rxd b rxc a rxc b cts a cts b dsr a dsr b dcd a dcd b dtr a dtr b rts a rts b dte_rts/dce_cts dte_dtr/dce_dsr dte_dsr/dce_dtr dte_dcd/dce_dcd dte_cts/dce_rts dte_ri/dce_ll tm dte_tm/dce_rl ll dte_ll/dce_ri rl ll rl ri tm dte_rl/dce_tm db-25 connector
18 ltc2845 sn2845 2845fs package descriptio n u g36 ssop 0802 0.09 ?0.25 (.0035 ?.010) 0 ?8 0.55 ?0.95 (.022 ?.037) 5.00 ?5.60** (.197 ?.221) 7.40 ?8.20 (.291 ?.323) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.50 ?13.10* (.492 ?.516) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 2.0 (.079) 0.05 (.002) 0.65 (.0256) bsc 0.22 ?0.38 (.009 ?.015) millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ?5.7 7.8 ?8.2 recommended solder pad layout 1.25 0.12 g package 36-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640)
19 ltc2845 sn2845 2845fs information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 5.00 0.10 (2 sides) note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 0.40 0.10 37 1 2 38 bottom view?xposed pad 5.15 0.10 (2 sides) 7.00 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh) qfn 0303 0.50 bsc 0.200 ref 0.200 ref 0.00 ?0.05 recommended solder pad layout 3.15 0.10 (2 sides) 0.18 0.18 0.23 0.435 0.00 ?0.05 0.75 0.05 0.70 0.05 0.50 bsc 5.20 0.05 (2 sides) 3.20 0.05 (2 sides) 4.10 0.05 (2 sides) 5.50 0.05 (2 sides) 6.10 0.05 (2 sides) 7.50 0.05 (2 sides) 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package u package descriptio uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701)
20 ltc2845 sn2845 2845fs lt/tp 0703 1k ? printed in usa ? linear technology corporation 2002 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts part number description comments ltc1321 dual rs232/rs485 transceiver two rs232 driver/receiver pairs or two rs485 driver/receiver pairs ltc1334 single 5v rs232/rs485 multiprotocol transceiver two rs232 driver/receiver or four rs232 driver/receiver pairs ltc1343 software-selectable multiprotocol transceiver 4-driver/4-receiver for data and clock signals ltc1344a software-selectable cable terminator perfect for terminating the ltc1543 (not needed with ltc1546) ltc1345 single supply v.35 transceiver 3-driver/3-receiver for data and clock signals ltc1346a dual supply v.35 transceiver 3-driver/3-receiver for data and clock signals ltc1543 software-selectable multiprotocol transceiver terminated with ltc1344a for data and clock signals, companion to ltc1544 or ltc1545 for control signals ltc1544 software-selectable multiprotocol transceiver companion to ltc1546 or ltc1543 for control signals including ll ltc1545 software-selectable multiprotocol transceiver 5-driver/5-receiver companion to ltc1546 or ltc1543 for control signals including ll, tm and rl ltc1546 software-selectable multiprotocol transceiver 3-driver/3-receiver with termination for data and clock signals ltc2844 3.3v software-selectable multiprotocol transceiver 3.3v supply, 4-driver/4-receiver companion to ltc2846 for control signals including ll ltc2846 3.3v software-selectable multiprotocol transceiver 3.3v supply, 3-driver/3-receiver with termination for data and clock signals, generates the required 5v and 8v supplies for ltc2846 and companion parts ltc2847 software-selectable multiprotocol transceiver 3-driver/3-receiver with termination for data and clock signals. with 3.3v digital interface seperate supply for digital interface works down to 3.3v u typical applicatio d2 d1 ltc2845 rts dtr dsr dcd cts d3 r2 r1 r3 ll ri tm rl txd scte txc rxc rxd 2 14 24 11 15 12 17 9 3 1 4 19 20 623 22 5 13 8 10 18 * 21 25 7 16 d4 d5 r4 r5 ltc2846 d1 d2 d3 r1 r2 r3 t t t t t *optional 2845 ta01 rts a (105) rts b dtr a (108) dtr b cts a (106) sg (102) shield (101) db-25 connector dcd a (107) dcd b dsr a (109) dsr b ll a (141) ri a (125) tm a (142) rl a (140) cts b scte b scte a (113) txd b txd a (103) txc a (114) txc b rxc a (115) rxc b rxd a (104) rxd b dte or dce multiprotocol serial interface with db-25 connector

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